The invention generally pertains to a novel production method and the resulting optoelectronic devices. More particularly, the invention pertains to a novel method of producing optoelectronic devices, such as vertical cavity surface emitting lasers (VCSELs) and providing isolated contacts for these devices, enabling their use in high speed, low cost multi-device arrays.
Smart pixel arrays (SPAs) are devices containing arrays of vertical cavity surface emitting lasers (VCSELs) and photodetectors. SPAs are capable of performing high-speed switching and routing of digital data. The increased capabilities of SPAs require increased switching speeds and low bit error rate. This in turn requires the interconnections between devices to have low parasitic capacitance. Otherwise, the capacitance reduces switching speed and increases the bit error rate due to noise integrated on the photodetector.
Normally, the devices making up a SPA have anode and cathode contacts, one on the top and one on the bottom of the device. However, for practical low cost assembly, it is preferable to have both contacts on one side (usually the non-emitting side) of the wafer. This enables the SPA to be easily flip-chip bonded to the integrated circuit that interfaces with the SPA.
Thus, it is necessary to use a through-wafer via to bring the one contact to the opposite side of the device. This configuration may be the largest contributor to parasitic capacitance, due to the proximity of the signal line to the common substrate. The parasitic capacitance of the structure is substantial because of the large surface area of the anode pad. However, the size of the anode pad cannot be reduced without compromising yield of the flip-chip interconnect process. To counteract this problem, protons are implanted between the VCSEL devices. Although this reduces the parasitic capacitance, it does not eliminate it or reduce it to an acceptable level.
The structure of SPAs also generally require the anode of the VCSEL to be driven instead of the cathode because the cathodes are common to all of the VCSELs when using the conventional N-type substrate. VCSELs driven by their anodes are undesirable because it requires use of slower P-channel transistors. Therefore, it is desirable to have a SPA structure in which the anode is on the same surface as the cathode and neither anode nor cathode is electrically common to the substrate.
Devices with both sources and detectors can often suffer from xe2x80x9ccross-talkxe2x80x9d. This creates an undesirable situation where, for example, the source can alter the detected response and thereby change the perceived signal. This problem can be solved by electrically isolating the source and detector. Therefore, there exists a need for a device that is capable of electrically isolating multiple components with anode and cathode on the same surface while still maintaining low parasitic capacitance.
The following summary of the invention is provided to facilitate an understanding of some of the innovative features unique to the present invention, and is not intended to be a full description. A full appreciation of the various aspects of the invention can be gained by taking the entire specification, claims, drawings, and abstract as a whole.
In accordance with the invention, there is provided a device including a top surface and a bottom surface, a through wafer via extending from the top to the bottom surface, optoelectronic structure and an isolation moat positioned so that the optoelectronic structure and the through wafer via are enclosed within the isolation moat.
In accordance with another aspect of the invention, there is provided a device having a top and bottom surface, that includes a vertical cavity surface emitting laser, at least two anodes positioned on the top and bottom surfaces of the device, a through wafer via extending from the top surface to the bottom surface with an electrically conductive material deposited on the inner walls that electrically connect the two anodes, an isolation moat positioned to enclose the vertical cavity surface emitting laser and the through wafer via, and a moat ion implantation region positioned below the isolation moat.
In accordance with the invention, there is also provided a method of producing a device including the steps of forming an optoelectronic configuration, forming a through wafer via extending from the top surface to the bottom surface, forming an isolation moat, wherein the through wafer via and the optoelectronic structure are enclosed by the isolation moat.
The invention provides production methods and the resulting optoelectronic devices. The optoelectronic devices produced from the method of the invention are particularly well suited for use in device arrays. Devices that can be produced by the method of the invention include, for example, VCSELs, p-n junction (PIN) detectors, and other optoelectronic devices. The preferred devices are VCSELs and are preferably part of an array, an SPA. The devices of the invention are advantageous for inclusion in arrays of the devices because they decrease the parasitic capacitance that limit the effectiveness of the arrays. Parasitic capacitance is decreased by the use of an isolation moat as described herein.
The novel features of the present invention will become apparent to those of skill in the art upon examination of the following detailed description of the invention or can be learned by practice of the present invention. It should be understood, however, that the detailed description of the invention and the specific examples presented, while indicating certain embodiments of the present invention, are provided for illustration purposes only because various changes and modifications within the scope of the invention will become apparent to those of skill in the art from the detailed description of the invention and claims that follow.